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XR18W750
WIRELESS UART CONTROLLER
REV. 1.0.0
3.7
INT (IRQ#) Output
The INT interrupt output changes according to the operating mode and enhanced features setup. Table 4
and 5 summarize the operating behavior for the transmitter and receiver. When operating in the Motorola bus
mode, the IRQ# output is the opposite polarity of the INT output. Also see Figures 16 through 21 .
T ABLE 4: INT P IN O PERATION FOR T RANSMITTER
FCR B IT -0 = 0
(FIFO D ISABLED )
FCR B IT -0 = 1 (FIFO E NABLED )
INT Pin
LOW = a byte in THR
HIGH = THR empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or FIFO empty
T ABLE 5: INT P IN O PERATION F OR R ECEIVER
FCR B IT -0 = 0
(FIFO D ISABLED )
FCR B IT -0 = 1
(FIFO E NABLED )
INT Pin
LOW = no data
HIGH = 1 byte
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
3.8
Programmable Baud Rate Generator
The enhanced UART has a programmable Baud Rate Generator (BRG) for the transmitter and receiver. The
divisor values for the specific data rates are given in the table below.
T ABLE 6: UART D ATA R ATES
3.9
Transmitter
Data Rate
300
600
2400
4800
9600
19200
38400
57600
115200
230400
D IVISOR FOR 16x
Clock
(Decimal)
3333.333
1666.667
416.667
208.333
104.167
52.083
26.042
17.361
8.681
4
DLM V ALUE
(HEX)
0D
06
01
00
00
00
00
00
00
00
DLL V ALUE
(HEX)
05
82
A0
D0
68
34
1A
11
8
4
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
3.9.1
Transmit Holding Register (THR) - Write Only
12
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